1. Field of the Invention
The present invention relates to the field of integrated circuit, more specifically, CMOS based integrated circuits. The present invention relates to providing various electrical protections to a CMOS integrated circuit.
2. Art Background
It is a well known fact that, under certain conditions, a parasitic pnpn junction would be created in a CMOS integrated circuit, resulting in the latchup and possibly destruction of the CMOS integrated circuit. For certain CMOS integrated circuits receiving power supply from more than one source, i.e. power being supplied through the inputs as well as from the V.sub.cc pins, one of such conditions is the power being supplied in an improper sequence. Particular examples of such CMOS integrated circuits are CMOS integrated circuits in a processor module with their V.sub.cc pins coupled to an in-circuit emulator (ICE), and their inputs coupled to an ISA bus having a number of drivers with large current delivery capacity.
Traditionally, integrated circuit designers have often relied on the fact that typically the operating characteristics of a CMOS integrated circuit are insufficient to surpass the high current threshold for triggering a latchup. The potential problem is simply ignored. Other times when the operating characteristics of a CMOS integrated circuit are sufficient to surpass even the high current threshold and trigger a latchup, it is often left up to the user to ensure that the power is applied in proper sequence.
Alternatively, a fuse or a polyfuse may be employed to protect the CMOS integrated circuit. A polyfuse is a self-closing circuit breaker. The use of a low cost one time fuse has the disadvantage of having to have the fuse replaced, each time it is blown. Such a requirement is often unacceptable, particularly in situations where the CMOS integrated circuits are used in a novice end user application, such as personal computer or consumer electronics. On the other hand, the use of a polyfuse has the disadvantages of being more costly, and having to wait for it to recloses.
As a further alternative, an intervening protection circuitry may be provided to enforce the sequence in which the power is to be applied. However, a practical intervening protection circuitry for a VLSI environment must be low in economic cost as well as hardware real estate cost.
On the other hand, it will be desirable if a low cost intervening protection circuitry could nevertheless provide protection against potential damages resulted from reverse current being sourced from one of the power supply to another power supply being deenergized unexpectedly. An intervening protection circuit between the deenergized power supply and the CMOS integrated circuits, in conjunction with the CMOS integrated circuits, may behave in such a manner, that allows current to be sourced from the drivers of the still energized power supply to the deenergized power supply. Since a deenergized power supply looks like a low impedance to ground, the drivers of the still energized power supply, the CMOS integrated circuits, as well as the intervening protection circuit itself could be strained beyond their maximum current ratings.
Furthermore, for CMOS integrated circuits comprising volatile SRAM-based software-downloaded Field Programmable Gate Array (FPGA), it will also be desirable if the low cost intervening protection circuit could also protect these SRAM-based FPGA from destructive reconfiguration as a result of low voltage.
As will be disclosed, the present invention provides a method and apparatus for providing various electrical protections to a CMOS integrated circuit that achieves the above described desired results.